In order to electrically insulate the terminal regions of the emitter and base in bipolar transistors from one another, in principle two methods are available: firstly, the terminal regions may be defined with the aid of photolithography for the emitter and base regions and be patterned with the aid of etching technology. Such transistors are therefore called aligned transistors. The distance between emitter and base terminal is then given by the minimum available lithography width. Since lithographic methods can only achieve resolutions of as far as 0.1 μm, this method is not suitable for scaled bipolar transistors in which the emitter is only a few 0.1 μm wide and the insulation region between the emitter and base should be even significantly smaller (typically a few 10 nm). Moreover, in the case of an alignment of emitter to base plane, an asymmetry always occurs in the current flow since, on account of the alignment tolerance of emitter to base plane, one side of the emitter is always nearer to the base terminal zone than the opposite side. Aligned transistors are therefore unsuitable for modern scaled, very high-performance transistors.
Almost all present-day transistors are therefore embodied as transistors that are self-aligned through an emitter window. The emitter and base terminal regions are formed in this case by polysilicon layers isolated from one another by a dielectric (silicon oxide or silicon nitride), for which reason they are also referred to as DPSA (double polysilicon self-aligned) transistors.
The dielectric is formed as a “spacer”, that is to say produced by anisotropically etching back a layer deposited over the whole area, so that the spacers remain as etching residues in the emitter window. In this case, the spacer width is determined by the thickness of the spacer layer and may therefore be significantly smaller than structures produced by lithographic methods (in principle just a few nm; a few ten 10 nm are typical nowadays). Therefore, this method is suitable for the production of extremely scaled DPSA transistors.
The DPSA transistor may contain both an implanted Si base and a epitaxially deposited SiGe base. The collector is usually connected via a buried layer buried in the substrate (also referred to as subcollector). On account of its lateral and vertical scalability and the small parasitic capacitance and resistance components, the DPSA transistor structure is best suited to very high speed applications.
DPSA transistors and corresponding production methods are disclosed, e.g. in T. F. Meister et al., IEDM Technical Digest 1995, p. 739-741 or in T. H. Ning et al., Self-Aligned Bipolar Transistor for High-Performance and Low-Power-Delay VLSI, IEEE Transactions on Electron Devices, Vol. ED-28, No. 9, pp. 1010-1013, 1981 or in DE 199 58 062 C2.
FIG. 2 is a schematic illustration of a known DPSA transistor as disclosed in T. F. Meister et al., IEDM Technical Digest 1995, p. 739-741.
In FIG. 2, reference symbol 1 designates a silicon semiconductor substrate, 10 designates an n+-type subcollector region in the form of a buried layer, 20 designates p+-type channel blocking regions, 25 designates an n−-type collector region, 30 designates a p-type base region, 35 and 35a designate a respective CVD insulation oxide layer, 15 designates a LOCOS insulation oxide layer, 40 designates a p+-type base terminal, 45 designates an n+-type collector contact, 55 designates a double spacer comprising silicon oxide/silicon nitride, and 60 designates an n+-type emitter contact.
FIGS. 3a-c are schematic illustrations of the method steps with regard to the emitter contact with oxide spacer insulation of a customary method for the production of a DPSA transistor, in contrast to FIG. 2 reference symbol 55′ designating this single spacer made of oxide. Reference symbol F designates the emitter window in the layers 35 and 40.
In order to produce the n+-type emitter contact, in the case of the DPSA transistor, after the formation of the oxide spacer 35′ covering the side walls of the emitter window F, on the active p+-type base region, an n+-doped (implanted or doped in situ) n+-type polysilicon layer 60 is applied in polycrystalline fashion on the active transistor zone and also on the surrounding insulation regions.
Afterward, the n+-type polysilicon layer 60 is patterned anisotropically by means of a phototechnology for the purpose of forming the final emitter contact 60 and the n+-type dopant is driven e.g. 20 nm into the underlying monocrystalline Si material of the base region 30 by means of a thermal step (FIG. 3c). This gives rise to an n+-type emitter composed of a monocrystalline portion 31 and a polycrystalline portion 60, between which is situated a very thin natural oxide layer 36 that forms after the spacer etching.